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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:40:58 11/28/2010 
-- Design Name: 
-- Module Name:    ps_reg - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.constants.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ps_reg is
	port (
		clk			: in std_logic;
		reset		: in std_logic;
		
		sel			: in std_logic;
		we			: in std_logic;
		
		parallel_in	: in std_logic_vector(DATA_SIZE-1 downto 0);
		serial_out	: out std_logic
	);
end ps_reg;

architecture Behavioral of ps_reg is
	signal mux_out, reg_out : std_logic_vector(DATA_SIZE-1 downto 0) := (others => '0');
	component REG32 is
	port (
		data_in		:	in std_logic_vector(DATA_SIZE-1 downto 0);
		data_out	:	out std_logic_vector(DATA_SIZE-1 downto 0);
		we			:	in std_logic;
		clk			:	in std_logic;
		reset		:	in std_logic
	);
	end component;
	
	component mux is
    	Port ( in0 : in  STD_LOGIC;
           in1 : in  STD_LOGIC;
			  sel : in STD_LOGIC;
           out0 : out  STD_LOGIC);
	end component;
begin
	-- purpose : input selection
	-- type    : sequential
	mux_gen : for I in 0 to DATA_SIZE-1-1 generate
		mux21 :
		mux
		port map (
			in0 => parallel_in(I),
			in1 => reg_out(I+1),
			sel => sel,
			out0 => mux_out(I)
		);
	end generate;
	
	-- purpose : input between 0 and the input bit 
	-- type    : sequential
	mux21_1 :
	mux
	port map (
		in0 => parallel_in(DATA_SIZE-1),
		in1 => '0',
		sel => sel,
		out0 => mux_out(DATA_SIZE-1)
	);
	
	-- purpose : Storage of the register value
	-- type    : structural
	reg :
		reg32
		port map(
			data_in		=> mux_out,
			data_out	=> reg_out,
			we			=> we,
			clk			=> clk,
			reset		=> reset
		);
	serial_out <= reg_out(0);
end Behavioral;

